1. Of the judgment of the court of first instance, prohibition, destruction, or payment exceeding the following portions prohibited, discarded, or payable.

1. Basic facts

A. The Plaintiff’s J chips development 1) The Plaintiff is a company that produces and sells the Plaintiff’s semiconductor circuits or various semiconductor circuits and MCU (only an exclusive protocol to control the specific system). 2) The Plaintiff’s researchers employed on August 1, 2005 and left office on March 23, 2007, and were in charge of the design and development of the semiconductor circuits (the director, on November 30, 201, retired on July 1, 2005), E (the retired company employed on August 1, 2005) (the retired on July 31, 201), E (the retired company) and the F (the F) were employed on August 1, 2005, and were in charge of the design and development of the semiconductor integrated circuits.

3) The Plaintiff via the said researchers (hereinafter “G”).

H The semiconductor chips (hereinafter referred to as “schips”) are only called “schips.”

(B) The Plaintiff registered the creation of semiconductors used in J chips pursuant to Article 21(1) of the Act on the Layout-Design of Semiconductors (hereinafter “Semiconductor Design Act”) as indicated below, while manufacturing and selling I chips in line. B. The Plaintiff registered the creation of semiconductors used in J chips as indicated below, pursuant to Article 21(1) of the Semiconductor Design Act.

(hereinafter) If a layout-design established and registered as described below is specified, the term “a layout-design” and the registered right shall be referred to as “a layout-design right.” The registration number of the name as of the registration date of the name is registration, J K K LM NP PP PP NT QV Qu Qu AB AB AB AH AH AB AI 2) V layout-design is part of the J chip LON circuits (Lowop Outs, supply a stable voltage and electricity to an internal circuit requiring a voltage lower than the input voltage, and a stable voltage and electricity to ensure the initial voltage when the initial pressure is increased. A layout-design is part of the PPR circuit (PPR), during a stable operation of the J chips at a specific initial voltage when the initial voltage is guaranteed.